`include "../rtl/top_soc.v"
module tb_add;

reg clk;
reg rst_n;

wire x3 = tb_add.u_open_soc_tb_add1.u_top_risc_open_soc_1.u_regs_top_risc_1.regs[3];
wire x26 = tb_add.u_open_soc_tb_add1.u_top_risc_open_soc_1.u_regs_top_risc_1.regs[26];
wire x27 = tb_add.u_open_soc_tb_add1.u_top_risc_open_soc_1.u_regs_top_risc_1.regs[27];

always #10 clk = ~clk;

initial
	begin
		clk <= 1'b1;
		rst_n <= 1'b0;
		#10
		 rst_n <= 1'b1;
	end

// initial
// 	begin
// 		$dumpfile("wave.vcd"); // 指定用作dumpfile的文件
// 		$dumpvars; // dump all vars
// 	end

//rom
initial
	begin
		$readmemh("D:/desktop/risc_v/generated/rv32ui-p-blt.txt", tb_add.u_open_soc_tb_add1.u_rom_open_soc_1.rom_mem);
	end
// reg time1;
// initial
// 	begin
// 		time1 <= 1'b1;
// 		#150
// 		time1 <= 1'b0;
// 	end
integer r;
initial
	begin
		// while (1)
		// 	begin
		// 		@(posedge clk)
		// 		 $display("x27 value is %d", tb_add.u_open_soc_tb_add1.u_top_risc_open_soc_1.u_regs_top_risc_1.regs[27]);
		// 		$display("x28 value is %d", tb_add.u_open_soc_tb_add1.u_top_risc_open_soc_1.u_regs_top_risc_1.regs[28]);
		// 		$display("x29 value is %d", tb_add.u_open_soc_tb_add1.u_top_risc_open_soc_1.u_regs_top_risc_1.regs[29]);
		// 		$display("-------------------------------------");
		// 	end
		wait(x26 == 32'b1);

		#200
		if (x27 == 32'b1)
			begin
				$display("--------------pass-----------");
			end
		else
			begin
				$display("-------------fail------------");
				for (r = 0;r < 31;r = r + 1)
					begin
						$display("x%2d value is %d", r, tb_add.u_open_soc_tb_add1.u_top_risc_open_soc_1.u_regs_top_risc_1.regs[r]);
					end
			end
	end

open_soc u_open_soc_tb_add1(
             .clk ( clk ),
             .rst_n ( rst_n )
         );

endmodule

    // Local Variables:
    // verilog-library-directories:("D:/desktop/risc_v/rtl")
    // End:
